My publications

From LinksWiki

Book, Book Chapters, and Book Sections

Resource-Driven Optimizations for Transient-Fault Detecting Superscalar Microarchitecture
Jie Hu, Greg M. Link, Johnsy John, Shuai Wang, Sotirios G. Ziavras
In Lecture Notes in Computer Science, Volume 3740, Published by Springer-Verlag in 2005. ISBN 3-540-29643-3

Networks on Chip: Interconnects for the Next Generation Systems-On-Chip
T. Theocharides, G. M. Link, N. Vijaykrishnan, and M. J. Irwin
In Advances in Computers, Vol. 63, Kluwer Academic Publishing, The Netherlands, 2005. ISBN 0-12-012163-8 , Volume 63

Journal Publications

A Holistic Approach to Designing Energy-Efficient Cluster Interconnect
E. J. Kim, G. M. Link, K. H.Yum, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and C. R. Das
In the IEEE Transactions on Computers, Volume 53, Number 6, June 2005. PDF

Conference Publications

Load Miss Prediction - Exploiting Power Performance Trade-offs
K. Malkowski, G. Link, P. Raghavan and M. J. Irwin
Proceedings of the 21st IEEE International Parallel and Distributed Symposium, IPDPS'07, High-Performance, Power-Aware Computing Workshop.

Thermally Robust Clocking Schemes for 3D Integrated Circuits
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg Link, Vijaykrishnan Narayanan and Yehia Massoud
Proc. of the IEEE Design Automation and Test in Europe, DATE, 2007.

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg Link, Vijaykrishnan Narayanan and Yehia Massoud
Proc. of the IEEE Symposium on Quality Electronic Design, ISQED, 2007.

Thermal Trends in Emergent Technologies
Link, G. M. and Vijaykrishnan, N.
To appear in International Symposium on Quality Electronic Design (ISQED) 2006, San Jose, CA , March 2006.

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
Hung, W.-L. and Link, G. M. and Xie, Y. and Vijaykrishnan, N. and Irwin, M. J.
To appear in International Symposium on Quality Electronic Design (ISQED) 2006, San Jose, CA , March 2006.

Resource-Driven Optimizations for Transient-Fault Detecting Superscalar Microarchitectures
Hu, J. S. and Link, G. M. and John, J. K. and Wang, S. and Ziavras, S. G.
In the Proceedings of the Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC) 2005, October 2005. PDF

Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
Hung, W.-L., Xie, Y. Link, G. M. and Conner, J.
In the Proceedings of the International Conference on Computer Design (ICCD), October 2005. PDF

Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip
G. M. Link and N. Vijaykrishnan
In the Proceedings of Design Automation and Test in Europe (DATE) 2005. PDF

Implementing LDPC Decoding on Networks on Chip
T. Theocharides, G. M. Link, N. Vijaykrishnan, M. J. Irwin
In the Proceedings of the 18th International Conference on VLSI Design, India, January 2005 PDF

FD-HGAC: A Hybrid Heuristic/Genetic Algorithm Hardware/Software Co-synthesis Framework with Fault Detection.
J.Conner,Yuan Xie, M. Kandemir, R. Dick, G. Link
Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC)., pp. 709-712, Jan. 2005. (99 regular papers accepted out of 692 submissions (14.3%))

A Generic Reconfigurable Neural Network Architecture Implemented as a Network On Chip
T. Theocharides, G. M. Link, N. Vijaykrishnan, M. J. Irwin, and V. Srikantam
In the Proceedings of the IEEE System on Chip Conference (SoCC, formerly ASIC) 2004. PDF

Fault Tolerant Algorithms for Network-On-Chip Interconnect
M. Pirretti, G. Link, R. R. Brooks, N. Vijaykrishnan, M.Kandemir, M. J. Irwin
In the Proceedings of ISVLSI 2004, Lafayette, LA, Feb 2004 PDF

Evaluating Alternative Implementations for LDPC Decoder Check Node Function
T. Theocharides, G. Link, E. Swankoski, N. Vijaykrishnan,M. J. Irwin, H.Schmit
In the Proceedings of ISVLSI 2004, Lafayette, LA, Feb 2004 PDF

Embedded Hardware Face Detection
T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, W.Wolf
In the Proceedings of the International Conference on VLSI Design, Mumbai, India, Jan 2004.  PDF

Energy Optimization Techniques in Cluster Interconnects
Kim, E. J., K.H. Yum, G. Link, N. Vijaykrishnan, M. Kandemir, M. Yousif, and M. J. Irwin and C. R. Das
In the Proceedings of International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003. PDF

This is by no means a comprehensive list, but instead all I could find on short notice. Expect more later...